This invention relates generally to semiconductor devices and, specifically, to charge storage devices and methods for forming the same. Even more specifically, this invention relates to capacitors and a method for forming them as they are used in decoupling devices, charge pumps, delay elements, regulators, and the like.
Oftentimes, the formation of capacitors as part of semiconductor circuitry involves (1) forming an oxide layer over a semiconductive substrate, such as a silicon substrate; (2) forming a plate over the oxide; and (3) doping the active area around the plate. The plate/oxide/substrate combination acts as a capacitor, which can serve many uses in semiconductor circuitry. For example, when placed in electrical communication with the connection pads of a die, such a capacitor can be used to filter voltage transients which may be generated by lead frame connection wires that also lead to the connection pads. In such cases, it is beneficial to form a depletion mode capacitor, wherein, between steps (1) and (2), a depletion well is implanted under the plate site with dopants of the same type as the dopants that are to be used in step (3) but at a lesser concentration. As a result, the depletion well is depleted of current carriers (electrons or holes).
As another example, capacitors can be used as part of a charge pump, which provides a current at a potential greater than the potential initially supplied to the circuit. Charge pumps often comprise an oscillator coupled to a capacitor. The capacitor, in turn, is coupled to an output node leading to other circuitry, such as a memory array. As the capacitor receives a signal from the oscillator that rises in voltage, the charge held by the capacitor is pumped to a level above VCC (commonly referred to as VCCP). This charge is subsequently discharged to the output node and used to drive circuitry external to the oscillator.
In a third example, capacitors can be used in delay circuitry, such as RC delay circuits. In such circuits, a resistive element is interposed between an input node and an output node, and one plate of the capacitor is coupled to the output node and to the resistive element, with the other plate coupled to a reference voltage node. The output node""s ability to respond to a change in voltage at the input node is delayed by the charging or discharging of the capacitor during that change.
As yet another example, capacitors can be incorporated into various types of regulator circuits such as reference voltage regulators. Examples of such can be found in U.S. Pat. No. 5,513,089 (FIG. 6 and accompanying text) and U.S. Pat. No. 5,581,206.
Regardless of the particular use for a capacitor, there is a constant need in the art to increase capacitance without increasing the die area used by the capacitor. It would also be desirable to maintain or even increase capacitance as the size of capacitors decreases in order to help fit more die on one wafer.
It is noteworthy that, in determining the capacitance of a storage device, prior art often focuses on the capacitance generated between the parallel portions of opposing plates, otherwise known as parallel capacitance. Nevertheless, it is also known that fringe capacitance exists at the sides of the plates and results from the non-uniform electric field at those sides. Further, it is known that this fringe capacitance can play a factor in increasing the total capacitance of a storage device. For example, in U.S. Pat. No. 4,931,901, two plates located side-by-side are added to the existing plates and are used to xe2x80x9cfine tunexe2x80x9d the total capacitance by allowing relatively small increases in the total capacitance of the storage device. As another example, U.S. Pat. No. 5,583,359, by Ng et al., discloses a capacitor having interleaved platesxe2x80x94wherein the material of one plate extends into a gap within the other plate. The capacitance between the extended portion of the first plate and the laterally adjacent sides of the other plate serves to increase the total capacitance to a point beyond that demonstrated by prior art capacitors with non-interleaved plates.
Another method for increasing capacitance is to create microstructures on the surface area of one of the electrodes, such as by forming hemispherical silicon grain (HSG) thereon. U.S. Pat. No. 5,554,557, by Koh, describes such a method. The bottom electrode consists of a conductive layer with HSG deposited thereon. In the disclosed LPCVD process, grains having a diameter of about 800 angstroms are formed on the conductive layer. (Koh at column 6, lines 45-56.) A dielectric is then conformally layered onto the HSG at a thickness ranging from 40 to 60 angstroms. (Koh at column 6 line 63-column 7 line 7.) Finally, the top electrode is formed over the dielectric. (Koh at column 7, line 8.) However, given the general size of the grains, the conformal nature of the overlying materials, and the thinness of the dielectric, the top electrode extends into the gap defined by the grains of the bottom electrode. As a result, capacitors using HSG are analogous to the interleaved plates discussed above.
In calculating the capacitance between non-interleaved plates, however, fringe capacitance is often disregarded in the prior art. See, for example, DAVID HALLIDAY and ROBERT RESNIK, FUNDAMENTALS OF PHYSICS 620 (1988 3d ed.).
The current invention provides a gap within a conductive member of a charge storage device, such as a capacitor. Regardless of whether this gap is termed a slot, slit, cavity, bore, trench, nonconformity, discontinuity, or other designation, it is an opening sized in relation to the dimensions of the capacitor""s components so that the fringe capacitance between the sides of the gap and the opposing non-interleaved conductive member results in at least as much capacitance per a unit of measurement as results from parallel capacitance. In some embodiments, the gap is in the form of an elongated groove or slot extending through a conductive plate of the capacitor. In one embodiment of this type, the slot is aligned along the width dimension of the plate, whereas another embodiment may have the slot aligned perpendicular to the width. Still another embodiment has an orientation somewhere between the two alignments described above. In other embodiments, there is a plurality of slots within the conductive plate. These embodiments include ones wherein there are slots intersecting each other. Additional embodiments include capacitor plates with gaps having a shape other than slots, such as cylinder-shaped gaps. Included in these types of embodiments are capacitor plates with a single non-slot gap and capacitor plates with multiple non-slot gaps. Combinations of slots and non-slot gaps on one plate are also within the scope of the invention, as are gaps that do not extend completely through the thickness of the plate. Moreover, the current invention also includes methods for forming the embodiments described above.
In distinction from devices having interleaved electrodes, including those devices that interleave on a small scale, such as HSG capacitors, the current invention includes within its scope embodiments wherein one electrode defines an opening that is separate from or does not include, surround, envelop, or intersect with the other electrode. Also covered are embodiments comprising a capacitor electrode having a surface that is generally conformal to the surface of another electrode (to the extent necessary to maintain parallel capacitance) except for at least one nonconformity. Also included are embodiments wherein one capacitor plate is generally continuous for purposes of generating parallel capacitance with a corresponding plate, with the exception of a discontinuity included within the capacitor plate. In one such exemplary embodiment, the face of one capacitor plate is planar and parallel to the face of the corresponding plate (which is also planar) except for a nonparallel portion. In a more specific embodiment, this nonparallel portion is vertically offset from the corresponding plate and, in an even more specific embodiment, is perpendicular to the corresponding plate.
Concerning distinctions from HSG capacitors in particular, the invention""s embodiments include those that are generally free of texture or microstructures to the extent that such textures or microstructures are not deliberately created and, if they exist as an inherent result of the creation process, do not substantially contribute to the total capacitance.